ROAD EXTRACTION VLSI PROCESSOR BASED ON AN OPTIMAL ALLOCATION AND ITS APPLICATION TO HIGHLY SAFE INTELLIGENT VEHICLES

In this paper, the authors present a collision warning system that is based on a fail-safe concept in which a warning is issued to a driver if a safe path cannot be found within a set amount of time. A road extraction VLSI process based on a logic-in-memory architecture is offered for solving the data-transfer bottleneck between memories and processing elements. In order to support the required bandwidth that is imposed by processing elements, an optimal memory allocation is suggested where data to be accessed simultaneously are distributed between different memory modules.

• Availability:
  • Find a library where document is available. Order URL: http://worldcat.org/oclc/21259390
• Supplemental Notes:
  • Publication Date: June 2001
• Corporate Authors:

  Tohoku Daigaku

  ,    
• Authors:
  • Hariyama, M
  • Kudoh, T
  • Kameyama, M
• Publication Date: 2001

Language

• Japanese

Media Info

• Pagination: p. 531-539
• Serial:
  • Denshi Joho Tsushin Gakkai ronbunshi. D-I, Joho, shisutemu I--konpyuta = The transactions of the Institute of Electronics, Information and Communication Engineers. D-I. Vol. J84D-I, no. 6
  • Publisher: Tohoku Daigaku

Subject/Index Terms

• TRT Terms: Crash avoidance systems; Emergency communication systems; Information processing
• Subject Areas: Data and Information Technology;

Filing Info

• Accession Number: 00823751
• Record Type: Publication
• Source Agency: UC Berkeley Transportation Library
• Files: PATH
• Created Date: Feb 5 2002 12:00AM