TRAFFIC RESPONSIVE RAMP CONTROL THROUGH THE USE OF MICROCOMPUTER

The research was involved in the investigation, development, and implementation of ramp control hardware and software through the use of microcomputer. A prototype controller consisting of a 4-bit Intel microprocessor and 2096 x 8 bit of programmable read-only-memory was developed for exploratory study. It was concluded that the second generation N-MOS microprocessors have superior instruction power and hardware capabilities than their P-MOS predecessors. The Type 140 Controller design specification was prepared under this research. The first 200 units of the Type 140 Controller, have been purchased for implementation. Programs for traffic responsive ramp control have been developed to be implemented with the Type 140 Controller.

• Corporate Authors:

  California Department of Transportation

  Transportation Laboratory
  5900 Folsom Boulevard
  Sacramento, CA  United States  95819

  Federal Highway Administration

  1200 New Jersey Avenue, SE
  Washington, DC  United States  20590
• Authors:
  • Fong, B C
• Publication Date: 1977-2

Media Info

• Pagination: 126 p.

Subject/Index Terms

• TRT Terms: Automatic control; Central processing units (Computers); Computer memory; Computer programming; Computer programs; Computers; Design; Freeways; Highway traffic control; Microcomputers; Ramp metering; Random access memory; Real time control; Software; Specifications; Traffic control; Traffic engineering
• Uncontrolled Terms: Hardware
• Old TRIS Terms: Central processing units; Computer systems hardware; Random access computer storage; Read only storage; Real time operation
• Subject Areas: Design; Highways; Operations and Traffic Management;

Filing Info

• Accession Number: 00167105
• Record Type: Publication
• Source Agency: National Technical Information Service
• Report/Paper Numbers: FHWACA-TL-1639-77-04Final Rpt., 631639
• Files: NTIS, TRIS, USDOT, STATEDOT
• Created Date: Nov 9 1978 12:00AM