This document describes tests conducted on the Discrete Address Beacon System (DABS) engineering model sensor with the release 6.4 software package to measure the performance characteristics of the computer subsystem distributive architecture. Tests were conducted for various aircraft load conditions in three specific areas: system data bus contention, global memory address space utilization, and processor utilization. Both the methods of conducting these tests and the results obtained are described. It was concluded that system data bus contention is not a problem with the distributive architecture used. Release 6.4 of the DABS software uses less than 20,480 words of the available 24,576 global memory address space in 24 of the 29 active processors. This leads to the conclusion that no problem should be experienced in expanding the size of the processor local memories from 8,192 words to 12,288 words. Additionally, an expansion of the local memories to 16,384 words appears feasible with minor software changes. The expansion of local memory will enable each processor to perform more functions. This will reduce the total number of processors required and lead to less complexity and a smaller overall volume for DABS. (Author)

  • Supplemental Notes:
    • See also AD-A085 585.
  • Corporate Authors:

    Federal Aviation Administration

    William J. Hughes Technical Center, Airport Technology Research and Development Branch
    Atlantic City International Airport
    Atlantic City, NJ  United States  08405

    Federal Aviation Administration

    800 Independence Avenue, SW
    Washington, DC  United States  20591
  • Authors:
    • Fisher, D
    • Pino, J
    • Fox, D
  • Publication Date: 1981-4

Media Info

  • Pagination: 58 p.

Subject/Index Terms

Filing Info

  • Accession Number: 00337951
  • Record Type: Publication
  • Source Agency: National Technical Information Service
  • Report/Paper Numbers: FAA-CT-81-7, FAA-RD-81-12
  • Files: NTIS, USDOT
  • Created Date: Aug 15 2002 12:00AM