An Intelligent Vehicular Traffic Signal Control System with State Flow Chart Design and FPGA Prototyping

The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.


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  • Accession Number: 01632820
  • Record Type: Publication
  • Files: TRIS
  • Created Date: Apr 28 2017 10:39AM