DESIGN OF A PARALLEL VLSI PROCESSOR FOR ROAD EXTRACTION BASED ON LOGIC-IN-MEMORY ARCHITECTURE

This paper describes the design of a road extraction VLSI (Very Large Scale Integration) processor that is designed to keep the data transfer bottleneck between processing elements to a minimum. It involves a algorithm that is based on parallel processing and logic- in-memory architecture.

• Supplemental Notes:
  • Publication Date: November 2000
• Corporate Authors:

  Hachinobe National College of Technology

  ,    
• Authors:
  • Kudoh, T
  • Hanyu, T
  • Kameyama, M
• Publication Date: 2000

Language

• Japanese

Media Info

• Pagination: p. 1009-1018
• Serial:
  • Keisoku Jido Seigyo Gakkai ronbunshu = transactions of the Society of Instrument and Control Engineers. Vol. 36, no. 11
  • Publisher: Hachinobe National College of Technology

Subject/Index Terms

• TRT Terms: In vehicle sensors; Parallel processing
• Subject Areas: Data and Information Technology;

Filing Info

• Accession Number: 00814808
• Record Type: Publication
• Source Agency: UC Berkeley Transportation Library
• Files: PATH
• Created Date: Aug 20 2001 12:00AM