METHOD OF PROGRAM SYNTHESIS FOR FAILSAFE INTERLOCKING DEVICE IN RAILWAY SIGNALLING

The functions are analyzed of conventional interlocking relay devices used for train control. It is indicated which parts should be designed on the failsafe basis. A method is also proposed for synthesizing a failsafe logic system which is fed with non-failsafe inputs. A universal digital computer program using an interlocking matrix is proposed for the failsafe logic system. The effectiveness of the proposed method has been confirmed by field tests and 20,000-hour test operations.

• Availability:
  • Find a library where document is available. Order URL: http://worldcat.org/issn/04247760
• Corporate Authors:

  Scripta Publishing Corporation

  Investment Building
  Washington, DC  United States  20005
• Authors:
  • Okumura, I
• Publication Date: 1974-11

Media Info

• Features: References;
• Pagination: p. 96-102
• Serial:
  • Electrical Engineering in Japan
  • Volume: 94
  • Issue Number: 6
  • Publisher: Scripta Technica, Incorporated
  • ISSN: 0424-7760

Subject/Index Terms

• TRT Terms: Electrical relays; Fail safe systems; Information processing; Planning; Traffic signal control systems
• Old TRIS Terms: Computerized planning; Electric relays; Interlocking; Signal systems
• Subject Areas: Planning and Forecasting; Railroads;

Filing Info

• Accession Number: 00135181
• Record Type: Publication
• Source Agency: Engineering Index
• Files: TRIS
• Created Date: Jul 13 1976 12:00AM